1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to an SRAM (Static Random Access Memory) and a method for manufacturing the same.
2. Description of the Related Art
FIG. 27 shows an equivalent circuit diagram of an SRAM memory cell. A load transistor Q5 and a driver transistor Q3 form an inverter. A load transistor Q6 and a driver transistor Q4 form an inverter. The inverters are electrically connected to each other to form a flip-flop.
A transfer transistor Q2 connects an output cell node 1000 of the inverter that is formed by the load transistor Q6 and the driver transistor Q4 and a bit line (BL). A gate electrode of the transfer transistor Q2 is electrically connected to a word line.
Source regions of the load transistors Q5 and Q6 electrically connect to a power supply line VDD. Source regions of the driver transistors Q3 and Q4 electrically connect to a ground line Vss.
A transfer transistor Q1 connects an output cell node 1002 of the inverter that is formed by the load transistor Q5 and the driver transistor Q3 and a bit line (/BL). A gate electrode of the transfer transistor Q1 is electrically connected to a word line.
The flip-flop retains a state in which the cell node 1000 is at a voltage of 3V, for example, and the cell node 1002 is at a voltage of 0V, for example, as xe2x80x9c1xe2x80x9d, for example. Also, the flip-flop retains a state in which the cell node 1000 is at a voltage of 0V, for example, and the cell node 1002 is at a voltage of 3V, for example, as xe2x80x9c0xe2x80x9d, for example.
An SRAM may suffer a problem of an xcex1-ray soft error. Materials for wiring layers, molding resin, and the like contain a very small amount of radioactive substances. The radioactive substances generate xcex1-rays. The xcex1-ray soft error is a phenomenon in which retained data is destroyed due to the xcex1-ray. The destruction of retained data by the xcex1-ray soft error will be described below in detail, with reference to the accompanying figure.
FIG. 25 is a cross-sectional view of a silicon substrate 200 in which the load transistor Q6 and the driver transistor Q4 are formed. The silicon substrate 200 is of a p-type. An n-well 202 and a p-well 204 are formed adjacent to each other. A source 212 and a drain 214 of the driver transistor Q4 are formed in the p-well 204. A p-type well contact region 216 is formed in the p-well 204. The well contact region 216 is isolated from the source 212 by a field oxide film 206. The well contact region 216 and the source 212 are electrically connected to the ground line Vss.
A source 218 and a drain 220 of the load transistor Q6 are formed in the n-well 202. An n-type well contact region 222 is formed in the n-well 202. The well contact region 222 is isolated from the source 218 by a field oxide film 210. The well contact region 222 and the source 218 are electrically connected to the power supply line VDD. The drain 220 is isolated from the drain 214 by a filed oxide film 208.
Next, the destruction of retained data by the xcex1-ray soft error will be described with reference to FIGS. 25 and 26. As shown in FIG. 25, when the cell node 1000 is at 3V, for example, the drain 214 is at 3V, and the p-well 204 is biased to the ground line Vss. Therefore, because a diode formed by the drain 214 and the p-well 204 is inversely biased, a depletion layer is formed.
In this state, if an xcex1-ray passes through the drain 214 and the p-well 204 and reaches the silicon substrate 200, the depletion layer of the diode is warped by the xcex1-ray. As a result, electron-hole pairs are cut along the pass of the xcex1-ray. As shown in FIG. 26, the holes flow into the well contact region 216 and into the ground line Vss. The electrons flow into the drain 214 that is at a high voltage. The flows of the holes and the electrons lower the drain voltage. As a result, the retained data is destroyed. In other words, in this example, the state of the cell node 1000 changes from 3V to 0V, and therefore the state xe2x80x9c1xe2x80x9d changes to xe2x80x9c0xe2x80x9d.
It is an object of the present invention to provide a semiconductor memory device with a structure that is difficult to cause harmful effects on the memory function and a method for manufacturing the same.
In accordance with one embodiment of the present invention, a semiconductor memory device has a semiconductor substrate defining a main surface, and a peripheral circuit region and an SRAM memory cell region in the main surface. The semiconductor memory device comprises a first well, a second well of a first conductivity type, a third well of a second conductivity type, a device element isolation structure, an embedded layer of the second conductivity type, a driver transistor, a load transistor, and an impurity region of the second conductivity type. The first well is formed in the peripheral circuit region, and the second well is formed in the memory cell region. The second well is shallower than the first well. The driver transistor is formed in the second well. The impurity region is formed in the second well. The impurity region is a drain of the driver transistor. The impurity region is an element that composes a cell node. The third well is formed in the memory cell region. The third well is shallower than the first well. The load transistor is formed in the third well. The device element isolation structure is formed in the memory cell region. The device element isolation structure isolates the driver transistor from the load transistor. The second well and the third well are formed to extend to a location under the device element isolation structure. The embedded layer is formed under the second well and under an area where at least the impurity region is located. The embedded layer forms a junction with the second well. The embedded layer is fixed at a potential that prevents carriers of the second conductivity type in the embedded layer from flowing into the second well.
The semiconductor memory device in accordance with the embodiment achieves the following advantages.
The miniaturization of a memory cell must address two conflicting issues. The length of the device element isolation structure (such as a semi-recessed LOCOS oxidation layer) of the memory cell area needs to be shortened in order to miniaturize the memory cell. On the other hand, to prevent the generation of a parasitic MOS leak current that causes latch-up, the spacing between one well and source/drain of another well formed adjacent to the one well needs to be longer than a certain distance. Accordingly, when the length of the device element isolation structure is shortened to miniaturize the memory cell, the spacing between one well and the source/drain of another well formed adjacent to the one well may become too short to an extent that a parasitic MOS leak current may be readily generated. However, in accordance with the embodiment of the present invention, the length of the device element isolation structure can be reduced for the miniaturization of the memory cell, while the distance between one well and the source/drain of another well formed next to the one well can be prevented from becoming too short.
In a semiconductor memory device in accordance with one embodiment of the present invention, the wells in the peripheral circuit region and the wells in the memory cell region may be different in depth. In other words, the second and third wells formed in the memory cell region are shallower than the first well formed in the peripheral circuit region. Accordingly, this structure can reduce an overlapped area between the second well and the third well beneath the device element isolation structure. The reason for this will be described below in conjunction with the discussion of the embodiments. Accordingly, in a semiconductor memory device in accordance with the present invention, the length of the device element isolation structure can be reduced, while the distance between one well and the source/drain of another well formed next to the one well can be prevented from becoming too short.
In accordance with another embodiment of the present invention, the semiconductor memory device of the present invention further includes an embedded layer. The embedded layer is formed in an area under the second well where at least the impurity region is located. The embedded layer forms a junction with the second well. The embedded layer is fixed at a potential that prevents carriers of the second conductivity type in the embedded layer from flowing into the second well.
In the semiconductor memory device in accordance with the present invention, the embedded layer can prevent the generation of an xcex1-ray soft error that may occur in the impurity region of the driver transistor (an element that forms a cell node). For example, when the semiconductor substrate is of a p-type, the embedded layer is an n-type, the second well is of a p-type, and the impurity region is of an n-type, the following phenomenon occurs.
Let us consider a situation when the impurity region of the driver transistor (an element that forms a cell node) is, for example, at a voltage of 3V, and an xcex1-ray passes through the impurity region of the driver transistor, the second well, the embedded layer, and the semiconductor substrate. As a result, the electron-hole pairs are cut. It is believed that only electrons in the second well are drawn to the impurity region (element that forms a cell node) because of the presence of the p-n junction between the second well and the embedded layer. Electrons in the embedded layer and in the semiconductor substrate do not flow into the second well, because the embedded layer is fixed at a positive potential (a potential that prevents the electrons from flowing into the second well).
In the manner described above, only the electrons in the second well are drawn to the impurity region (element that forms a cell node). Accordingly, the voltage at the impurity region (element that forms a cell node) is difficult to become unstable, and, therefore, this makes the retained data difficult to be destroyed.
When a first embedded layer is an n-type, the impurity concentration of the first embedded layer is preferably 5E12-5E13 cmxe2x88x922. This impurity concentration is the same as the impurity concentration of a low resistance layer of the n-type first well.
In the embodiments of the present invention, the cell node refers to a node at which a transfer transistor and an output of an inverter that is formed by a load transistor and a driver transistor are connected to each other.
In accordance with the present invention, examples of the device element isolation structure include a LOCOS oxide film, a semi-recessed LOCOS oxide film, or a shallow trench (the depth ranging between about 0.4 and 0.8 xcexcm).
In accordance with the present invention, the xe2x80x9csource/drainxe2x80x9d refers to at least one of a source and a drain.
In a semiconductor memory device in accordance with another embodiment of the present invention, the following structure may be added. For example, the semiconductor memory device of the present invention includes another impurity region of the first conductivity type. The another impurity region is formed in the third well. The another impurity region is a drain of the load transistor. The another impurity region is an element that forms the cell node. The embedded layer is not formed in an area under the third well where the another impurity region is located. The semiconductor substrate is the first conductivity type.
As a result of the addition of the above-described structure, the generation of an xcex1-ray soft error that may occur in the another impurity region of the load transistor (an element that forms a cell node) can be prevented. For example, when the semiconductor substrate is of a p-type, the embedded layer is n-type, the third well is of an n-type, and the another impurity region is of a p-type, the following phenomenon occurs.
Let us consider a situation where the another impurity region of the load transistor (an element that forms a cell node) is, for example, at a voltage of 0V, and an xcex1-ray passes through the another impurity region of the load transistor, the third well, and the semiconductor substrate, with the result that the electron-hole pairs are cut. As a result, it is believed that only holes in the third well are drawn to the another impurity region (element that forms a cell node) because of the presence of the p-n junction between the third well and the semiconductor substrate.
In this manner, since the embedded layer is not formed in an area under the third well where the another impurity region is located, only the holes generated in the third well among the holes generated by the xcex1-ray result in a soft error. Because the third well is relatively shallow, relatively few holes are generated therein. As a result, the voltage of the another impurity region is difficult to become unstable, and this makes the retained data difficult to be destroyed.
In the semiconductor memory device in accordance with the present invention, the following structure may be added. The semiconductor memory device of the present invention further includes a well contact region of the second conductivity type. The well contact region is formed in the third well, the well contact region is a contact region that fixes a well potential of the third well, and the embedded layer contacts the third well.
As a result of the addition of the above-described structure, the potential of the embedded layer can be fixed at a potential that can prevent the carriers of the second conductivity type in the embedded layer from flowing into the second well. For example, when a positive voltage is applied to the well contact region, electrons generated in the embedded layer in the example described above are drawn from the embedded layer through the third well to the well contact region.
In the semiconductor memory device in accordance with the present invention, the following structure may be added. For example, the semiconductor memory device in accordance with the present invention includes another embedded layer of the first conductivity type. The another embedded layer is formed under the second well, and the another embedded layer contacts the second well.
As a result of the addition of the structure described above, the generation of latch-up can be prevented. More specifically, the conductivity type of the another embedded layer is the same as the conductivity type of the second well, and, therefore, the resistance of the second well is lowered. This contributes to the prevention of the generation of latch-up. In one embodiment, when the another embedded layer is a p-type, the another embedded layer may have an impurity concentration of 5E12-5E13 cmxe2x88x922.
In the semiconductor memory device in accordance with the present invention, the first well, the second well, and the third well may be retrograded wells. The retrograded well is a well that is formed by a high-energy ion implantation without using a thermal diffusion.
Each of the first well, the second well, and the third well, that are retrograded wells, has a first concentration layer, a second concentration layer, and a third concentration layer in the order from a top layer. The first well further has a fourth concentration layer under the third concentration layer. The first concentration layer may be, for example, a channel dope layer that adjusts the threshold voltage (Vth) of the transistor. The second concentration layer may be, for example, a punch-through stopper layer that suppresses the short channel effect of the transistor. The third concentration layer may be, for example, a channel-cut layer that prevents the operation of a parasitic transistor. The fourth concentration layer may be, for example, a low resistance layer that lowers the well resistance. In one embodiment, in the second and third wells, the first concentration layer may be a channel dope layer, the second concentration layer may be a channel stopper layer, and the third concentration layer may be a channel cut layer, for example.
In the semiconductor memory device in accordance with the present invention, the length of the device element isolation region that isolates the wells in the memory cell region may fall within a range of about 0.2 xcexcm-1.6 xcexcm. The border between the second well and the third well needs to be located below the device element isolation structure. When the resist is patterned, a positional alignment error may occur. Accordingly, the device element isolation structure requires a certain minimum length. The minimum length of the structure may be about 0.2 xcexcm. Also, when the device element isolation structure has a length longer than about 1.6 xcexcm, the size of the memory cell becomes too large.
In the semiconductor memory device in accordance with the present invention, the second well and the third well may have a depth of about 0.5-1.2 xcexcm. When the second and third wells are shallower than about 0.5 xcexcm, the device element isolation structure becomes deeper than the wells. This presents a problem in designing as to how a well contact region for fixing the potential of the well is formed. When the second and third wells are deeper than about 1.2 xcexcm, the overlapped area between the second well and the third well, beneath the device element isolation structure, becomes greater.
In the semiconductor memory device in accordance with the present invention, the semiconductor substrate may be of a p-type. As a result, the p-type wells in the memory cell region are connected to one another through the semiconductor substrate, and, therefore, the resistance of the wells is lowered. As a result, this suppresses an increase in the substrate potential of a region, where the n-channel transistor (having a relatively large substrate current compared to the p-channel transistor) is formed.
In accordance with another embodiment of the present invention, a method is provided for manufacturing a semiconductor memory device having a semiconductor substrate defining a main surface, and a peripheral circuit region and an SRAM memory cell region in the main surface. The method includes the following steps. (a) A device element isolation structure is formed in the main surface. (b) A first well is formed by ion-implanting an impurity in the peripheral circuit region. (c) An embedded layer of a second conductivity type is formed by ion-implanting an impurity in the memory cell region. (d) A third well of the second conductivity is formed by ion-implanting an impurity in the memory cell region, wherein the third well is shallower than the first well, formed to extend to a location under the device element isolation structure, and in contact with the embedded layer. (e) A second well of the first conductivity type is formed by ion-implanting an impurity in the memory cell region. The second well is in contact with the third well in an area lower than the device element isolation structure, and is formed over the embedded layer. Also, the second well forms a junction with the embedded layer. (f) A driver transistor is formed in the second well. Among the impurity regions of the driver transistor, an impurity region that forms an element composing a cell node is formed in a manner that the embedded layer is located under the impurity region. (g) A load transistor is formed in the third well.
In the above-described embodiment of the present invention, a method is provided for manufacturing a semiconductor memory device that can prevent the distance between one well and source/drain of another well adjacent to the one well from becoming too short without excessively elongating the device element isolation structure.
In accordance with the present invention, an embedded layer is further formed, as described below. The embedded layer is formed in an area under the second well, under a region where the impurity region of the driver transistor (element that forms a cell node) is located, and forms a junction with the second well. Also, the embedded layer contacts the third well.
In the method for manufacturing the semiconductor memory device in accordance with the present invention, in step (b) and step (c), a resist pattern having a thickness of about 3.0 xcexcm-8.0 xcexcm is used as a mask, and in step (d) and step (e), a resist pattern having a thickness of about 1.2 xcexcm-2.5 xcexcm is used as a mask.
If the thickness of the resist pattern is thinner than about 3.0 xcexcm in steps (b) and (c), the impurity penetrates the resist pattern when the ion implantation is performed to form a retrograded well. If the thickness of the resist pattern is thicker than about 8.0 xcexcm, control of the configuration of the end portion of the resist pattern is difficult. As a result, a problem arises in which the length of the device element isolation structure needs to be increased.
If the thickness of the resist pattern is smaller than about 1.2 xcexcm in steps (d) and (e), the impurity penetrates the resist pattern when the ion implantation is conducted to form a retrograded well. If the thickness of the resist pattern is greater than about 2.5 xcexcm, the control of the configuration of the end portion of the resist pattern is difficult. As a result, a problem arises in which the overlapped area between the second well and the third well below the device element isolation structure becomes greater.
Either a positive resist or a negative resist works as the resist pattern in steps (b) and (c). Also, a positive resist or a negative resist works as the resist pattern in steps (d) and (e). However, more preferably, a positive resist may be used. This is because the positive resist outperforms the negative resist in the control of the vertical configuration of the end portion of the resist pattern and the dimensional control of the resist pattern.
In the method for manufacturing the semiconductor memory device in accordance with the present invention, the step of implanting ions in step (b) includes the step of implanting ions in step (c).
In the method for manufacturing the semiconductor memory device in accordance with another embodiment of the present invention, the following features may be added where the first well is a twin-well having a well of a first conductivity type and a well of a second conductivity type. Step (b) includes implanting ions in a region where the well of the first conductivity type is formed and implanting ions in a region where the well of the second conductivity type is formed, and step (d) includes implanting ions three times in a region where the third well is formed and in a region where the well of the second conductivity type in the peripheral circuit region is formed. The step of implanting ions three times forms the third well having a third concentration layer, a second concentration layer and a first concentration layer, in the order from a bottom layer, in the memory cell region. Step (b) and the step of implanting ions three times form the well of the second conductivity type having a fourth concentration layer, a third concentration layer, a second concentration layer and a first concentration layer, in the order from a bottom layer, in the peripheral circuit region. Furthermore, step (e) includes implanting ions three times in a region where the second well is formed and a region where the well of the first conductivity type in the peripheral circuit region is formed. The step of implanting ions three times forms the second well having a third concentration layer, a second concentration layer and a first concentration layer, in the order from a bottom layer, in the memory cell region; and step (b) and the step of implanting ions three times form the well of the first conductivity type having a fourth concentration layer, a third concentration layer, a second concentration layer and a first concentration layer, in the order from a bottom layer, in the peripheral circuit region.
In the method for manufacturing the semiconductor memory device in accordance with the present invention, the following step (h) may be added. For example, step (h) includes forming another embedded layer of the first conductivity type under a region where the second well is formed.
According to this manufacturing method, the semiconductor memory device has another embedded layer of the first conductivity type, wherein the another embedded layer is formed under the second well, and the another embedded layer contacts the second well.
In the method for manufacturing the semiconductor memory device in accordance with the present invention, the step of implanting ions in step (b) includes implanting ions in step (h).